A 13.42ps Resolution, Low-Power Time-to-Digital Converter and 0.519fJ Energy-Efficient Novel Voltage-to-Time Converter for High-Speed Time-Based ADC Application

Voltage domain ADC architectures require high gain and bandwidth opamps to amplify the signal for successive stages. The opamp design gets a bit challenging due noise, small lower overdrive voltage. Due these limitations, inclination shifted towards high-speed converters which don’t opamps. Time based Analog Digital Converters (TBADC) is one such category of circuits. TBADCs are constituted from VTC followed by TDC with an encoder in end. This work concerned around high-resolution time digital converter (TDC) proposing novel high-speed, low power consuming voltage (VTC) circuit. Both circuits were implemented Cadence Virtuoso EDA tool version 6.1.7 Spectre was employed running simulations. had resolution 13.425 ps consume 1.873 μW. Process corner analysis Monte Carlo performed on determine worst possible deviations performance. proposed exhibited delay 23.79 consumption 21.83 μW at 1 Volt. presented can be used time-based Converters.